A PCI Express board designed to interface with the electronic phase-2 upgrades of the ATLAS detectors at CERN

Nei prossimi 10 anni è in previsione un aggiornamento radicale dell'acceleratore LHC al CERN finalizzato al raggiungimento di più alti valori di luminosità istantanea (oltre \begin{math}5 \times 10^{34}cm^{-2}s^{-1}\end{math}) ed integrata (oltre un fattore 10 rispetto a quella attuale). Conseguentemente, anche i rilevatori degli esperimenti che lavorano al CERN, così come i loro sistemi di acquisizione dati, dovranno essere aggiornati per poter gestire un flusso notevolmente maggiore rispetto a quello utilizzato finora. Questa tesi tratta in particolare di una nuova scheda elettronica di lettura, progettata e testata nel laboratorio di elettronica del Dipartimento di Fisica ed Astronomia dell'Università di Bologna e nel laboratorio di elettronica della Sezione INFN (Istituto Nazionale di Fisica Nucleare) di Bologna. Le motivazioni che hanno indotto lo sviluppo della scheda prototipale sono molteplici. Un primo obiettivo da perseguire è stato quello di aggiornare la versione attuale delle schede elettroniche di acquisizione dati usate oggi nel Pixel Detector dell'esperimento ATLAS, visto che sono anch'esse sotto la responsabilità della sezione INFN di Bologna. Secondariamente, la scheda (nominata Pixel-ROD) è orientata a gestire le esigenze elettroniche che seguiranno l'upgrade di LHC durante la fase 2. La complessità del progetto e l'inerzia intrinseca di una vasta collaborazione come quella di ATLAS, hanno poi indotto lo sviluppo di questo progetto elettronico in largo anticipo rispetto al vero upgrade di fase 2 di LHC, previsto per il 2024. In questo modo saranno anche più facilmente eseguibili eventuali aggiornamenti tecnologici in corso d'opera, senza dover riprogettare da zero un sistema di acquisizione dati completo

Simulated Hough Transform Model Optimized for Straight-Line Recognition Using Frontier FPGA Devices

The use of the Hough transforms to identify shapes or images has been extensively studied in the past using software for artificial intelligence applications. In this article, we present a generalization of the goal of shape recognition using the Hough transform, applied to a broader range of real problems. A software simulator was developed to generate input patterns (straight-lines) and test the ability of a generic low-latency system to identify these lines: first in a clean environment with no other inputs and then looking for the same lines as ambient background noise increases. In particular, the paper presents a study to optimize the implementation of the Hough transform algorithm in programmable digital devices, such as FPGAs. We investigated the ability of the Hough transform to discriminate straight-lines within a vast bundle of random lines, emulating a noisy environment. In more detail, the study follows an extensive investigation we recently conducted to recognize tracks of ionizing particles in high-energy physics. In this field, the lines can represent the trajectories of particles that must be immediately recognized as they are created in a particle detector. The main advantage of using FPGAs over any other component is their speed and low latency to investigate pattern recognition problems in a noisy environment. In fact, FPGAs guarantee a latency that increases linearly with the incoming data, while other solutions increase latency times more quickly. Furthermore, HT inherently adapts to incomplete input data sets, especially if resolutions are limited. Hence, an FPGA system that implements HT is inefficient for small sets of input data but becomes more cost-effective as the size of the input data increases. The document first presents an example that uses a large Accumulator consisting of 1100 x 600 Bins and several sets of input data to validate the Hough transform algorithm as random noise increases to 80% of input data. Then, a more specifically dedicated input set was chosen to emulate a real situation where a Xilinx UltraScale+ was to be used as the final target device. Thus, we have reduced the Accumulator to 280 x  280 Bins using a clock signal at 250 MHz and a few tens input points. Under these conditions, the behavior of the firmware matched the software simulations, confirming the feasibility of the HT implementation on FPGA

Study and Optimization of Particle Track Detection via Hough Transform Hardware Implementation for the ATLAS Phase-II Trigger Upgrade

In the CERN of Geneva the Large Hadron Collider (LHC) will undergo several deep upgrades in the next years. Instantaneous and Integrated Luminosity will be increased respectively up to 5−7·10 34 cm −2 s −1 and 3000 f b −1 . Alongside this collider the experiments exploiting LHC will undergo through upgrades crucial to fulfill the HEP goals. The ATLAS upgrades are divided into phases, namely Phase-I and Phase-II. Part of the ATLAS upgrade concerns the Trigger and Data Acquisition systems. In particular, for the ATLAS trigger, a big technological update is planned for the Phase-II. My contribution to these Phase-I and Phase-II plans has been focused to the Trigger and Data Acquisition system electronic update. In the Phase-I upgrade I worked at the commissioning of the new FELIX readout cards FLX-712 which will be mounted on part of the TDAQ system. These cards are FPGA based with a bandwidth up to 480 Gb/s and exploit PCI Express Generation 3 technology. My work has been focused on the preparation and the follow up of part of the tests of the cards for quality checks and controls. The ATLAS Phase-II trigger targets to increase its output data stream to the Tier 0 of one order of magnitude. For the ATLAS Phase-II upgrade I developed an implementation of a tracking algorithm to fulfill the new trigger requirements. This algorithm, known as Hough Transform, is used to track particle trajectories and it has been already demonstrated to be suited for the ATLAS specifications. In this thesis I present the study, the simulations and the hardware implementation of a preliminary version of the Hough Transform algorithm on a XILINX Ultrascale+ FPGA device

A high throughput Intrusion Detection System (IDS) to enhance the security of data transmission among research centers

Data breaches and cyberattacks represent a severe problem in higher education institutions and universities that can result in illegal access to sensitive information and data loss. To enhance the security of data transmission, Intrusion Prevention Systems (IPS, i.e., firewalls) and Intrusion Detection Systems (IDS, i.e., packet sniffers) are used to detect potential threats in the exchanged data. IPSs and IDSs are usually designed as software programs running on a server machine. However, when the speed of exchanged data is too high, this solution can become unreliable. In this case, IPSs and IDSs designed on a real hardware platform, such as ASICs and FPGAs, represent a more reliable solution. This paper presents a packet sniffer that was designed using a commercial FPGA development board. The system can support a data throughput of 10 Gbit/s with preliminary results showing that the speed of data transmission can be reliably extended to 100 Gbit/s. The designed system is highly configurable by the user and can enhance the data protection of information transmitted using the Ethernet protocol. It is particularly suited for the security of universities and research centers, where point-to-point network connections are dominant and large amount of sensitive data are shared among different hosts.Comment: 10 pages, 10 figures, 16th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD23), 25-29 September 2023, Siena, Ital

General purpose readout board {\pi} LUP: overview and results

This work gives an overview of the PCI-Express board $\pi$LUP, focusing on the motivation that led to its development, the technological choices adopted and its performance. The $\pi$LUP card was designed by INFN and University of Bologna as a readout interface candidate to be used after the Phase-II upgrade of the Pixel Detector of the ATLAS and CMS experiments at LHC. The same team in Bologna is also responsible for the design and commissioning of the ReadOut Driver (ROD) board - currently implemented in all the four layers of the ATLAS Pixel Detector (Insertable B-Layer, B-Layer, Layer-1 and Layer-2) - and acquired in the past years expertise on the ATLAS readout chain and the problematics arising in such experiments. Although the $\pi$LUP was designed to fulfill a specific task, it is highly versatile and might fit a wide variety of applications, some of which will be discussed in this work. Two 7$^{th}$-generation Xilinx FPGAs are mounted on the board: a Zynq-7 with an embedded dual core ARM Processor and a Kintex-7. The latter features sixteen 12.5$\,$Gbps transceivers, allowing the board to interface easily to any other electronic board, either electrically and/or optically, at the current bandwidth of the experiments for LHC. Many data-transmission protocols have been tested at different speeds, results will be discussed later in this work. Two batches of $\pi$LUP boards have been fabricated and tested, two boards in the first batch (version 1.0) and four boards in the second batch (version 1.1), encapsulating all the patches and improvements required by the first version.Comment: 6 pages, 10 figures, 21th Real Time Conference, winner of "2018 NPSS Student Paper Award Second Prize

Iron Absorption following a Single Oral Dose of Ferrous Sulfate or Ferric Gluconate in Patients with Gastrectomy

Background: Iron deficiency anemia frequently occurs in gastrectomized patients. Methods: Serum iron levels following the ingestion of a single oral dose of 105 mg elemental iron, taken as ferrous sulfate (FeS) or ferric gluconate (FeG), have been evaluated in 20 gastrectomized patients (and 20 controls). All subjects participated on 2 different test days, 1 month apart: they took a single dose of 105 mg elemental iron as FeS or FeG after a night of fasting. Serum iron concentrations at baseline, 30, 60, 120 and 180 min after the oral dose administration were measured. Results: In patients and controls receiving FeG, serum iron levels did not significantly change. After oral ingestion of FeS, patients' serum iron levels gradually increased. The increase in serum iron levels was 148 and 168% at 120 and 180 min in patients (p < 0.0001 for both evaluations), whilst in controls, it was 216% at 120 min and 234% at 180 min, i.e. significantly higher than in gastrectomized patients (p < 0.001 for both evaluations). Conclusions: In gastrectomized patients, a single oral dose of FeS shows a significant increase in iron serum concentration, albeit lower than in controls. Further studies on a larger sample of patients will be necessary to confirm these results

Resting energy expenditure in adult patients with Crohn's disease.

SummaryBackground & aimsCrohn's disease (CD) is a chronic intestinal disorder of unknown etiology involving any section of the gastrointestinal tract often associated with protein-energy malnutrition (PEM). Increased resting energy expenditure (REE) unmatched by adequate dietary intake is amongst the pathogenetic mechanisms proposed for PEM. Aim of this study was to evaluate REE in CD patients receiving or not immuno-suppressive therapy as compared to controls.Methods36 CD patients (22 M and 14 F, age range 18–55 years) clinically stable and without complications since at least 6 month were studied. REE was evaluated by indirect calorimetry and body composition by BIA. Full biochemistry was performed. Patients were divided into two groups: Group 1 (G1 = 12 patients) without and Group 2 (G2 = 24 patients) with immuno-suppressive therapy.ResultsThe two groups were similar for age, height and BMI whereas significantly differed for weight (G1 vs G2: 56.9 ± 7.44 vs 62.3 ± 8.34 kg), fat free mass (FFM: 40.4 ± 5.73 vs 48.2 ± 7.06 kg), fat mass (FM: 17.0 ± 3.55 vs 13.9 ± 5.54 kg) and phase angle (PA: 5.6 ± 1.4 vs 6.5 ± 1.0°). Serum inflammation parameters were significantly higher in G1 than in G2: hs-PCR: 7.76 ± 14.2 vs 7.16 ± 13.4 mg/dl; alfa 2-protein: 11.7 ± 3.69 vs 9.74 ± 2.08 mg/dl; fibrinogen: 424 ± 174 vs 334 ± 118 mg/dl (p < 0.05). REE was higher in G2 vs G1: 1383 ± 267 vs 1582 ± 253kcal/die (p < 0.05) both in men: 1579 ± 314 vs 1640 ± 203 and women: 1267 ± 140 vs 1380 ± 132. Nevertheless, when corrected for FFM, REE resulted higher in G1 than G2 (34.8 ± 4.89 vs 33.0 ± 4.35 kcal/kg, p < 0.05) group, also higher compared to our, age and sex matched, control population (REE/FFM: 30.9 ± 4.5 kcal/kg).ConclusionsOur preliminary results show that REE when adjusted for FFM is increased in clinically stable CD patients and mildly reduced by immunosuppressive therapy possibly through a direct action on inflammation and on body composition characteristics